Semiconductor Engineering

Multi-die Testing In The Field Must Build On Established Test Methodologies

The AI revolution is significantly outpacing the IC industry’s ability to sufficiently test multi-chip systems for all necessary failure mechanisms at probe, final test, and system-level test. The ...
Semiconductor Engineering

Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s ...
GEN

Multi-Level Test Kits

VERICHEM LABORATORIES now offers two multi-level test kits of clinical reference materials for the calibration verification of Lithium assays. The kits, the Electrolyte Standard Kit (List No. 9200) ...
EDN

System-level test’s expanding role in producing complex chips

System-level test (SLT), once used largely as a stopgap measure to catch issues missed by automated test equipment (ATE), has evolved into a necessary test insertion for high-performance processors, ...