Hackaday

FPGA Used VHDL For Fractals

Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You ...
Yahoo Finance

Menta Follows FPGA Leaders by Selecting Verific for its SystemVerilog, VHDL Front End

ALAMEDA, CA--(Marketwired - Jul 2, 2014) - Verific Design Automation today announced Menta® selected its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers to serve as the front end to ...
Design-Reuse

Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements

Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Henderson, NV – January 20, ...
New Electronics

Faster FPGA verification

Launched in 2015, and used by about 20% of all VHDL FPGA designers, UVVM is one of the fastest growing verification methodologies in the EDA industry. Today, design verification accounts for more than ...
Yahoo Finance

Verific's SystemVerilog, VHDL Parsers Chosen by Flexras Technologies to Serve as Front End for FPGA-Based Prototyping Tool

ALAMEDA, CA--(Marketwired - Aug 5, 2014) - Verific Design Automation today announced Flexras Technologies, provider of high-performance partitioning software, has implemented its industry-standard, ...
Hackaday

FPGA Snake Game Uses No VHDL At All

We’re really not supposed to start a feature like this; but this hack is awesome. It’s a game of Snake implemented by an FPGA dev board. It uses a 16×16 LED matrix as the display and an SNES ...
Business Insider

GOWIN Semiconductor Adds VHDL Support to their GOWIN Synthesis FPGA Software for Complete RTL Language Support

SAN JOSE, Calif. and GUANGZHOU, China, March 31, 2020 (GLOBE NEWSWIRE) -- GOWIN Semiconductor Corp., the world’s fastest-growing programmable logic company, announces VHDL support for their GOWIN ...
Semiconductor Engineering

FPGA VHDL Verification

This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented ...
Electronic Design

Design Recipes For FPGAs

Looking at an FPGA to solve your problems? Need to learn VHDL? Then pick up Design Recipes For FPGAs by Peter Wilson. It is not an in-depth intro to VHDL and FPGA design. Instead, it’s a nice overview ...
EDN

Design Recipes for FPGAs – A Simple VGA Interface

Editor's Note: I was recently perusing a new book called Design Recipes for FPGAs that was written by Peter Wilson and published by Newnes (ISBN-13: 978-0750668453). This is a rather interesting “Cook ...